MOS transistors typically include a gate region, spacers situated on either side of the gate, and source and drain regions. The source and drain regions typically include a doped region in the substrate beside the gate, and also a lightly doped region (e.g., lightly doped drain (LDD) region) which is shallow and runs under the spacers to meet a region of the substrate situated under the gate. The substrate region under the gate corresponds to the channel in which the charge carriers move, and it is in contact with the source and drain regions. To form the source and drain regions, several dopant implantation steps are performed.
One application of interest for MOS transistors is for circuits which form artificial neural networks. Human neurons have a sigmoid response. This response may be reproduced by circuits including a plurality of conventional MOS transistors. For this purpose, reference may be made to the article by K. M. Hynna and K. Boahen entitled “Neuronal Ion-Channel Dynamics in Silicon”, IEEE International Symposium on Circuits and Systems, pp 3614-3617, IEEE Press, 2006, or to the article by Mukhlis and Yulisdin entitled “Design Of Neural Network Circuit Inside High Speed Camera Using Analog CMOS 0.35 ¼ m Technology”, Industrial Electronic Seminar, 2009, which describe complex circuits forming artificial neurons, in which each neuron is formed by several transistors.